Electronically variable capacitance

ABSTRACT

An electronically controlled capacitor utilizing an analog multiplier and to obtain an effect analogous to the Miller Effect. An input signal is fed through an input resistor which is connected to a fixed capacitor which is in turn coupled to a transistor in a common base configuration. An analog multiplier is capacitively coupled to the transistor&#39;&#39;s collector which drives the input side of the fixed capacitor through an output resistor.

United States Patent Zwirn et al.

[54] ELECTRONICALLY VARIABLE CAPACITANCE [72] Inventors: Robert Zwirn, Encino; Ralph E. A

Johnson, Canoga Park; Jacob M. Sacks, Palos Verdes Peninsula,- all of Calif. a

[73] Assignee: The United States ofAmerica as represented by the Secretary of the Air Force a .22 Filed: Nov. 17,1971

21 Appl.No.: 199,684

[52] us. c1. 4107/1119, 32o/1,323/74,

1511 .1111.c1.....; ..11o3111/1o [58] FieldofSearch ..307/ 109;320/l;333/80T; s34/ 14,- 7s; 323/74 [56] References Cited UNITED STATES PATENTS. I g 2,953,734 .9/1960 Leyde ..320/1 1151 3,702,405 [451- Nov. 7, 1972.

3,211,984 10/1965 A Jones ..320/1 3,551,846 12/1970 Hansen ..333/ 80T Primary Examiner-Stanley M. Urynowicz, Jr. Assistant Examiner-Stuart l-lecker Attorney-Harry A. Herbert, Jr. et al.

[57] ABSTRACT An electronically controlled capacitor utilizing an analog multiplier and to obtain an effect analogous to the MillerEffect. An input signal is fed through an input resistor which is connected to a fixed capacitor which is in turn coupled to a transistor in a common 4 base configuration. An analog multiplier is capacitively coupled to the transistors collector which drives the input side of the fixed capacitor through an output resistor. v

3 Claims, 5 Drawing Figures The present invention is anelectronically controlled capacitor which'is useful in suppressing video corresponding to clutter whose dimensions I aresignificantly smaller than the target dimensions.

In the past, the problem of varying the capacitances for the purpose of suppressing video clutter was approached by the discrete addition of capacitors to. the circuitat pre-set target-dimensions. A discussion of this technique can be found in the article, Development of Alternate Tracker for Maverick Missile, Hughes Aircraft Report No. P69-400, prepared by R. Zwirn, p. 4-1'9.

The present invention overcomes the limitations of the prior art because the controlis continuous and linear, the value of capacitance is always optimum for the instantaneous target dimensions. Also the tracking output is smooth, as opposed to containing steps which 1 occur due to instantaneous changes in delay when capacitors are switched in. I

SUMMARY OF THE INVENTION The circuit of the present invention is related to the well-known Miller effect with some significant differences. The Miller amplifier drives the bottom of a capacitorwhile in this invention an analog multiplier circuit drives the top in relation" to the input. Also the Miller effect output is related to the voltage applied to the capacitor while in the invention the analog multiplier circuit output is related to the current out of the capacitor and the analog multiplier circuit is coupled. I I

It is therefore an object of the invention to provide an improved. Miller effect typeci rcuit useful for sup- DESCRIPTION OF THE DRAWINGS FIGS 1 and 2 are circuit diagrams used for the'ex- .planation of the conventional Miller effect;

v 2 DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Referringto FIG. 1, there is shown a simplified, circuit showing theMiller effect. A voltage E is fed an input .11 through resistor 13 and voltage E is obtainedat output 15. Amplifier 16 having an amplifying factor of K drives the bottom of capacitor 17. The circuit of FIG. 1 is equivalent to the circuit of FIG. 2 which now includes effective capacitor 19 the value thereof depending on the value of K and the value of capacitor 17 with C C( 1+K).

An embodiment of the invention is shown in FIG. 3 where the voltage input E is impressed .at point 21 throughv input resistor 23. At node 25 the circuit divides and the current is then designated as i, and i Capacitor 27is connected between node ZSandemitter 29 of transistor 31. Resistors 32 and 34 control the bias of transistor 31. The output of transistor 31 taken from FIG. 3 is a circuit diagram showing a first embodiment of the invention;

FIG. 4 is a circuit diagram showing an equivalent circuit to FIG. 3; and i I v FIG. 5 is a circuit diagram showing a second embodiment of the invention.

collector 33 is coupled to analog multiplier 35 via capacitor 37. The input to analog multiplier 35 is designated as e Control voltage V is also fed to analog multiplier 35 and its output drives the top of capacitor 27 through output resistor 39 which has the same value as input resistor 23. The equivalent circuit of FIG. 3 is shown in FIG. 4 which. now includes effective variable capacitor 41 in parallel with fixed capacitor 27.

- The following equations describe circuit'operation.

selecting K, V 'R, and r, the capacitance can be'made to vary linearly over-a large dynamic range (typically greater than 60: l

An alternate embodiment of the invention is shown in FIG. 5 in which input voltage e is fed to mixer 43 and then to resistor 45'followed' by the parallel circuit of capacitor 47 and amplifier 49. The output or amplifier 49 is fed to analog divider 51 which is also fed by control voltage V The output of analog divider 51 is then fed to mixer 43. The analog divider is composed of an analog multiplier and an operational amplifier having amplifying factor K.

What is claimed is:

1. A capacitance control circuit comprising:

a. a capacitor having first and second terminals; b. an input resistor connected to the first terminal of the capacitor; c. a transistor having an emitter and collector, the

emitter being connected to the second terminal of 3 4 b. a resistor fed by the output of the mixer; input of the mixer. c. an amplifier fed by the output of the resistor; 3. A capacitance control circuit according to claim 2 d, a capacitor in shunt with the amplifie d wherein the analog divider comprises an operational e. an analog divider fed by the amplifier with the outamplifier and an analog mulllpllerput of the analog divider comprising the second 5 

1. A capacitance control circuit comprising: a. a capacitor having first and second terminals; b. an input resistor connected to the first terminal of the capacitor; c. a transistor having an emitter and collector, the emitter being connected to the second terminal of the capacitor; d. an analog multiplier capacitively coupled to the collector of the transistor; and e. an output resistor connected between the first terminal of the capacitor and the output of the analog multiplier.
 2. A capacitance control circuit comprising: a. a mixer having first and second inputs; b. a resistor fed by the output of the mixer; c. an amplifier fed by the output of the resistor; d. a capacitor in shunt with the amplifier; and e. an analog divider fed by the amplifier with the output of the analog divider comprising the second input of the mixer.
 3. A capacitance control circuit according to claim 2 wherein thE analog divider comprises an operational amplifier and an analog multiplier. 